A process of this type is carried out when a number of data processing units are to be connected by way of a single multiple line system. If the data processing units are processors then such a system is designated as a multiprocessor system. In order to simplify the following description, a data processing unit disconnectable on a multiple line system is therefore designated as a processor, although the connecting-in of other types of data processing units is conceivable also. Moreover the multiple line system will be referred to in the following as a "bus" in agreement with the terminology familiar to one skilled in the art.
Within a system constructed with such a bus, the individual processors or other data processing units which are to be connected with other processors are connected into the bus one after another in time. The sequence of this connecting-in is determined by one central or a number of local allocating units (arbiters) which operate in accordance with an algorithm stored in them. When a processor is to be connected into the bus, in order to be connected with another processor or with a global memory, it delivers a request signal by way of the bus, whereby the central or a local allocation unit is caused to allocate the bus to the requesting processor according to the algorithm stored in this unit, so that this processor can then be connected with the bus. When a number of processors transmit a request signal, then the allocation algorithm brings about a selection of one of the requesting processors, to which the bus is then allocated, so that it can hold it.
During the holding, the respective processor can correspond with and exchange information signals by way of the bus with other processors or data processing units such as memories or input/output devices. In order to keep the number of signal lines in the bus as small as possible, address signals and data signals are transmitted one after another in time during such a connection. For this, a flag signal is given as to whether the information signals transmitted are address signals or data signals, which is done by flag signals which are transmitted over other signal lines in the bus parallel to the address or data signals. Since such flag signals identify the type of the respective information signals transmitted, they are designated in the following as information type signals. The address or data signals in distinction from this are designated as information value signals.
The signal transmission on the bus can be carried out dependent on clock signals from a central bus clock generator. This facilitates maintaining the correct time sequence of the signals transmitted and makes possible a characterization with time of the validity of the information type signals and the information value signals. Besides this, the bus clock controls the mode of operation of the allocation, since the bus is to allocate a number of processors one after another by means of this clock.
A system of the type described above requires a relatively large number of bus signal lines. Although the very same signal lines are utilized for transmitting the address signals and the data signals, further signal lines are required for forming connections between the separate processors for the further functions discussed above of a flag, allocating, bus clock control and also of addressing, which further lines only fulfill control purposes, but cannot be utilized for information signal transmission proper. If the number of signal lines is reduced, then the operating speed of the system is also reduced.